This invention relates to drivers used in integrated circuits and more particularly to time variant drives for controlling driver transistors.
The high speed drivers which are improved by the present invention are of the type consisting of an N-channel MOS (NMOS) or P-channel (PMOS) driver transistor which is controlled by a digital drive signal to, in the case of an NMOS driver transistor, rapidly shunt to ground the current supplied to a data bus, or, in the case of a PMOS driver transistor, rapidly short the data bus to the positive power supply. Shown in FIG. 1 is a typical NMOS driver transistor 10 connected to data bus 15. When a "high" drive signal V.sub.G of voltage V.sub.max is applied to gate 10-G of driver transistor 10, driver transistor 10 turns on and becomes saturated, thus effectively shorting to ground bus 15. This shunting corresponds to a logical zero signal on bus 15 since bus 15 is pulled low (i.e., to about zero volts). The absence of shunting (i.e., when driver transistor 10 is open) allows a positive voltage to appear on bus 15, representing a logical one. The rapid switching of driver transistor 10 enables the rapid transfer of digital information from drive signal V.sub.G to devices connected to bus 15.
The design of high speed-high current bus drivers used in integrated circuits has encountered some limitations that have their bases in the laws of physics. When the data bus is shorted to ground by the driver transistor, the rapid change of current and voltage on the bus (i.e., voltage being driven "low") causes a damped oscillation or ringing, shown in FIG. 2, due to the inherent parasitic self-inductances of the leads connected to the driver transistor combined with the inherently capacitive loads of the devices connected to the bus. The equivalent bus circuit is shown in FIG. 3, where device leads 16, 18 have self-inductances represented by inductors 20, 22 and the capacitive load is represented by capacitor 24. The bus circuit, therefore, effectively forms an LC oscillator circuit, where L equals the combined inductance of leads 16, 18, and C equals the capacitance of the load, with a ringing frequency related to 1/(LC).sup.1/2, although this frequency is altered in actual circuits by additional factors. This damped ringing can cause unintentional triggering of devices connected to bus 15 if the amplitude of an oscillation cycle exceeds the logic threshold level of the devices. This situation is shown in FIG. 2 at time T, where V.sub.th is the logic threshold level of the devices.
Various approaches have been taken to eliminate the effect of these initial discharge transient currents. These approaches have limited the current through the driver transistor, thereby initially shunting to ground only part of the current supplied to the bus through the driver transistor and, consequently, reducing the amplitude of the ringing. This limited current through the driver transistor is then increased to the full current required to fully shunt to ground all the current supplied to the bus. The amount of current shunted at each stage is calculated to be insufficient to cause objectionable ringing on the bus.
One technique, shown in FIG. 4a, used to implement this approach is to use two MOS transistors 26, 28 in parallel as the driver, where transistor 26 only shunts to ground a portion of current supplied to bus 15 upon application of drive signal V.sub.G, while transistor 28 shunts to ground the remaining current supplied to bus 15 upon application of slightly delayed drive signal V.sub.G '. FIG. 4b shows the voltage (V.sub.out) applied to the devices connected to bus 15. A problem with this prior art technique is that a fairly complex digital logic network must be designed and incorporated into the integrated circuit to provide delayed drive signal V.sub.G '. Also, parallel drivers 26 and 28 must turn off quickly at the same time to avoid incurring two separate current surges on bus 15, which may, in conjunction, cause unintentional triggering of devices connected to bus 15. Another disadvantage is that the degree of ringing on the bus is a function of the sizes of drivers 26 and 28 (i.e., width-to-length ratio). Therefore, the extent of ringing on the bus is fixed once the drivers have been fabricated.
Another technique, shown in FIG. 5a, is used to provide a two-tiered drive signal to driver transistor 10, wherein the first tier is of a voltage V.sub.G1 sufficient to cause driver transistor 10 to shunt to ground only a portion of the current supplied to bus 15. The second tier is the addition of a slightly delayed voltage V.sub.G2, where the sum of V.sub.G1 and V.sub.G2 make driver transistor 10 fully conduct and shunt to ground all current supplied to bus 15. FIG. 5b shows the voltage (V.sub.out) supplied to the devices connected to bus 15.
The above described two-tiered drive signal generator is relatively complex due to its requiring two voltage sources, and, as in the circuit of FIG. 4a, requires the two voltage sources turn off simultaneously to avoid two separate current surges on bus 15.
FIG. 6 illustrates a typical output driver stage used in CMOS circuitry. In the circuit of FIG. 6, the positive supply voltage +V is not shorted to ground when current is to be shunted away from bus 15, as in FIGS. 1-5, but instead the bus is exclusively coupled to either +V or ground. Shown in FIG. 6 are NMOS driver transistor 30 and PMOS driver transistor 32, forming the output driver stage. The gate of NMOS driver transistor 30 is coupled to a pre-driver stage comprising NMOS transistor 34 and PMOS transistor 36, while the gate of PMOS driver transistor 32 is coupled to a pre-driver stage comprising NMOS transistor 38 and PMOS transistor 40. The gates of all transistors forming the pre-driver stage are made common and coupled to an input drive signal V.sub.in so that upon application of a sufficiently low V.sub.in pre-driver transistors PMOS 36 and PMOS 40 will conduct, causing +V to be applied to the gate of NMOS driver transistor 30 and PMOS driver transistor 32. NMOS driver transistor 30 will now fully conduct and drive bus 15 to approximately ground potential. When a sufficiently positive input drive signal V.sub.in is applied to the gates of the pre-driver transistors, only pre-driver transistor NMOS 34 and NMOS 38 will conduct, causing PMOS driver transistor 32 to turn on and drive bus 15 to approximately +V.